`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:00:12 03/31/2014 
// Design Name: 
// Module Name:    reg_file 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module reg_file(reg_1,reg_2,
					 R0,R1,R2,R3,R4,R5,R6,R7,
					 Rn,Ra,Rb,write_back,write,clk,reset);

output [15:0] reg_1,reg_2,R0,R1,R2,R3,R4,R5,R6,R7;
//output [15:0] pc_read,pc_out;
input [2:0] Rn,Ra,Rb;
input [15:0] write_back;
input write, clk, reset;
//input [15:0] pc_write;

////////////////////////////////

reg [15:0] REG[7:0];
//reg [15:0] pc;

//initial begin
//	pc = 16'd0;
//end

assign reg_1 = REG[Ra];
assign reg_2 = REG[Rb];
//assign pc_read = pc;
assign R0 = REG[0];
assign R1 = REG[1];
assign R2 = REG[2];
assign R3 = REG[3];
assign R4 = REG[4];
assign R5 = REG[5];
assign R6 = REG[6];
assign R7 = REG[7];
//assign pc_out = pc;

always @(posedge clk) begin
	if(reset == 1) begin
//		pc = 16'd0;
		REG[0] =15'd0;
		REG[1] =15'd0;
		REG[2] =15'd0;
		REG[3] =15'd0;
		REG[4] =15'd0;
		REG[5] =15'd0;
		REG[6] =15'd0;
		REG[7] =15'd0;
	end
//	else pc = pc_write;
		
	if(write == 1)
		REG[Rn] = write_back;
		 
	end
endmodule
